1. Field of the Invention
The present invention relates generally to output driver circuits for semiconductor integrated circuit devices, and more specifically, to an output driver circuit capable of restraining generation of noise. The invention has particular applicability to a semiconductor memory device.
2. Description of the Background Art
Generally, a plurality of semiconductor integrated circuit devices are placed on a printed circuit board, and their input/output terminals are connected one another through interconnections provided on the printed circuit board. Accordingly, when an output signal is output from a semiconductor integrated circuit device, an interconnection and another semiconductor integrated circuit device, i.e. a load connected to the output terminal (or output lead) is driven by the output signal.
Generally, an output driver circuit for driving a load connected to an output terminal is provided in the output stage of a semiconductor integrated circuit device. Loads connected to output terminals vary in size, therefore a large load is connected in some cases and a small load is connected in other cases. Transistors having a large mutual conductance (or current driving capability) are usually used in the final stage of an output driver circuit so that a large load can be driven.
The invention is generally applicable to an output driver circuit provided in the output stage of a semiconductor integrated circuit device, but applications of the invention to semiconductor memories will be described in the following by way of illustration.
FIG. 19 is a block diagram showing the circuit of a conventional static random access memory (hereinafter referred to as "SRAM"). Referring to FIG. 19, the SRAM 100 includes an address buffer 84 for receiving an X address signal XA and a Y address signal YA which are externally applied, an X decoder 85 and a Y decoder 86 for decoding the address signals XA and XA, a word line driving circuit 87 for driving word lines 3a to 3d, a column selection circuit 88 for selecting bit line pairs 6a, 6b to 9a, 9b, and a memory cell array 97 including memory cells MC each connected to a corresponding word line and a corresponding bit line pair.
The SRAM 100 further includes a local sense amplifier 89 for amplifying a data signal read out from a memory cell MC, a sense amplifier activation circuit 90 for activating the local sense amplifier 89, a writing amplifier 91 for amplifying an input data signal DI to be written, a data writing circuit 92 for writing a data signal in a memory cell MC, a main sense amplifier 94 for amplifying an output signal from the local sense amplifier 89, a clamp potential generation circuit 93 for applying a clamp potential to the main sense amplifier 94, a level conversion circuit 95 for converting a TTL level signal output from the main sense amplifier 94 into an MOS level signal, and an output driver circuit 96 for driving a load connected to an output terminal DQ in response to the converted signal. The line 100 also represents a semiconductor substrate.
In a data writing operation, the X address signal XA and the Y address signal YA are applied to the X decoder 85 and the Y decoder 86 through the address buffer 84. The X decoder 85 selectively activates one of the word lines 3a to 3d by decoding the X address signal XA. The Y decoder 86 selects one of the bit line pairs 6a, 6b to 9a 9b by decoding the Y address signal YA. The input data signal DI is provided to the data writing circuit 92 through the writing amplifier 91. The data writing circuit 92 amplifies the provided data signal and drives the bit line pair selected by the Y decoder 86. As a result, the input data signal DI is stored in the memory cell MC decided by the activated word line and the selected bit line pair.
In a reading operation, the X decoder 85 selectively activates one of the word lines 3a to 3d by decoding the externally applied X address signal XA. A data signal stored in the memory cell MC connected to the activated word line is applied on the respective bit line pairs 6a, 6b to 9a, 9b. The Y decoder 86 selects one bit line pair by decoding the externally applied Y address signal YA. Accordingly, a data signal on the one bit line pair is selectively applied to the local sense amplifier 89. The data signal amplified by the local sense amplifier 89 is provided to the main sense amplifier 94 and amplified therein.
The data signal amplified by the main sense amplifier 94 is limited within the range of a so-called TTL level, and therefore the level conversion circuit 95 conducts a level conversion from the TTL level to the MOS level. The converted data signal is provided to the output driver circuit 96, and the output driver circuit 96 in turn drives a load connected to the output terminal DQ in response to the applied signal.
FIG. 20 is a circuit diagram showing one example of a memory cell utilized in the SRAM 100 shown in FIG. 19. Referring to FIG. 20, the memory cell of a high resistance load type includes resistors R1, R2 having a high resistance value, NMOS transistors Q1, Q2 as a driving transistor, and NMOS transistors Q3, Q4 as an access transistor.
FIG. 21 is a circuit diagram showing another example of a memory cell utilized in the SRAM 100 shown in FIG. 19. Referring to FIG. 21, the CMOS memory cell includes a PMOS transistor Q5 provided in place of the resistors R1, R2 shown in FIG. 20, and NMOS transistors Q1 to Q4.
FIG. 23 is a circuit diagram showing the output driver circuit 96 shown in FIG. 19. Referring to FIG. 23, the conventional output driver circuit 96 includes a PMOS transistor 10 and an NMOS transistor 20 connected in series between a power supply potential Vcc and a ground potential Vss, an NAND gate 77 for supplying a control voltage to the gate of transistor 10, and an NOR gate 76 for applying a control voltage to the gate of transistor 20. A data signal RD output from the level conversion circuit 95 is applied to respective one inputs of NAND gate 77 and NOR gate 76. An externally applied output enable signal /OE is applied to the other input of NOR gate 76. The other input of NAND gate 77 receives the inverse of the output enable signal /OE from an inverter 79. The output terminal DQ is connected to a common connection node of the transistors 10 and 20.
In operation, when the output enable signal /OE of a low level is externally applied, the NAND gate 77 and the NOR gate 76 operate as inverters. More specifically, NAND gate 77 inverts the applied data signal RD and applies the inverted signal to the gate of transistor 10. The NOR gate 76 inverts the applied data signal RD and applies the inverted signal to the gate of transistor 20. As a result, one of the transistors 10 and 20 is selectively turned on in response to the data signal RD and the load connected to the output terminal DQ is driven.
When the output enable signal /OE is in a high level, the NAND gate 77 and the NOR gate 76 output output signals of a high level and a low level, respectively. In other words, regardless of the applied data signal RD, fixed potentials are provided to the gates of transistors 10 and 20. At that time, since the transistors 10 and 20 are turned off, the output terminal DQ is brought into a floating state (i.e. it is not driven).
As described above, since various loads (not shown) are connected to the output terminal DQ, the mutual conductance between transistors 10 and 20 (or current driving capability) is designed to be a value sufficient for driving these loads. Accordingly, when a large load is connected to the output terminal DQ, a large current flows through the output terminal DQ and the transistors 10 or 20.
FIG. 22 is a circuit diagram schematically showing a semiconductor memory actually installed on a printed wiring board. Referring to FIG. 22, the semiconductor memory 300 is connected between a power supply line Vcc and a ground line Vss. The semiconductor memory 300 receives an input data signal through a data input terminal DI, and drives a load 303 through the data output terminal DQ. A driving transistor in the output driver circuit of the semiconductor memory 300 has a mutual conductance large enough for driving the load 303, and therefore an output current Io flowing through the output terminal DQ has a waveform with sharp risings and fallings. In other words, the output current Io contains high frequency signal component. Therefore, parasitic inductances 301 and 302 which are not negligible exist with respect to the high frequency signal component between each power supply line Vcc and the ground line Vss as shown in FIG. 22. Assuming that the inductance values of parasitic inductances 301 and 302 are L, the voltage change .DELTA.V caused by the flow of the current Io through these parasitic inductances 301, 302 is given by the following equation: EQU .DELTA.V=L.multidot.(dIo/dt) (1)
The voltage change .DELTA.V given by equation (1) is transmitted to the power supply line Vcc and the ground line Vss as a noise, which will result in an erroneous operation in the semiconductor memory 300.
FIG. 24 is a signal waveform chart for use in illustration of such an erroneous operation in the semiconductor memory 300 shown in FIG. 22. Referring to FIG. 24, a write enable signal /WE rises at time t21, the voltage of output terminal DQ changes in response to an output data signal at time t22. Accordingly, the output current Io (not shown) flowing through the output terminal DQ is so steep that the potential of ground line Vss changes as illustrated in FIG. 24. As a result, the levels of input signals such as the write enable signal /WE and the output enable signal /OE change relatively to the ground level, resulting in an erroneous operation.
More specifically, in response to a change in the potential of the ground line Vss, the threshold voltage Vth of the buffer circuit receiving the externally applied write enable signal /WE, for example, changes relatively to a true ground level as represented by the chain dotted line in FIG. 24. Consequently, a detection of the signal WE being in a low level may be made in the semiconductor memory during the period from time t23 to time t24. As a result, an erroneous operation will be caused in the semiconductor memory.